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NS DESIG R NEW T PART D FO N ENDE PLACEME OMM D REData Sheet REC DE 14A NOT MMEN EE ISL90 S RECO
(R)
ISL9014
March 11, 2008 FN9245.3
Dual LDO with Low Noise, Low IQ and High PSRR
ISL9014 is a high performance dual LDO capable of sourcing 300mA current from both outputs. The device has a low standby current and high-PSRR and is stable with output capacitance of 1F to 10F with ESR of up to 200m. A reference bypass pin allows an external capacitor for adjusting a noise filter for low noise and high PSRR applications. The quiescent current is typically only 45A with both LDOs enabled and active. Separate enable pins control each individual LDO output. When both enable pins are low, the device is in shutdown, typically drawing less than 0.1A. Several combinations of voltage outputs are standard. Output voltage options for each LDO range from 1.5V to 3.3V. Other output voltage options may be available upon request.
Features
* Integrates two high performance LDOs - VO1 - 300mA output - VO2 - 300mA output * Excellent transient response to large current steps * Excellent load regulation: <1% voltage change across full range of load current * High PSRR: 70dB @ 1kHz * Wide input voltage capability: 2.3V to 6.5V * Extremely low quiescent current: 45A (both LDOs active) * Low dropout voltage: typically 200mV @ 300mA * Low output noise: typically 30VRMS @ 100A (1.5V) * Stable with 1F to 10F ceramic capacitors * Separate enable pins for each LDO * Soft-start to limit input current surge during enable * Current limit and overheat protection
Pinout
ISL9014 (10 LD 3X3 DFN) TOP VIEW
* 1.8% accuracy over all operating conditions * Tiny 10 Ld 3mmx3mm DFN package * -40C to +85C operating temperature range
10 VO1 9 8 7 6 VO2 NC NC GND
VIN EN1 EN2 CBYP NC
1 2 3 4 5
* Pin compatible with Micrel MIC2211 * Pb-free (RoHS compliant)
Applications
* PDAs, Cell Phones and Smart Phones * Portable Instruments, MP3 Players * Handheld Devices including Medical Handhelds
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005, 2006, 2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL9014 Ordering Information
PART NUMBER (Notes 1, 2, 3) ISL9014IRNNZ ISL9014IRNJZ ISL9014IRNFZ ISL9014IRNCZ ISL9014IRMNZ ISL9014IRMMZ ISL9014IRMGZ ISL9014IRLLZ ISL9014IRKNZ ISL9014IRKKZ ISL9014IRKJZ ISL9014IRKFZ ISL9014IRKPZ ISL9014IRKCZ ISL9014IRJNZ ISL9014IRJMZ ISL9014IRJRZ ISL9014IRJCZ ISL9014IRJBZ ISL9014IRGPZ ISL9014IRGCZ ISL9014IRFJZ ISL9014IRFDZ ISL9014IRFCZ ISL9014IRPLZ ISL9014IRPPZ ISL9014IRCJZ ISL9014IRCCZ ISL9014IRBLZ ISL9014IRBJZ ISL9014IRBCZ ISL9014IRBBZ NOTES: 1. Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. For availability and lead time of devices with voltage combinations not listed in the table, contact Intersil Marketing. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PART MARKING DCBS DBBK DBBL DCBT DCBV DBBV DCCC DCEA DCCG DBBW DCFA DBBM DDJA DCBA DCCH DBBT DCDA DBBP DCCA DDBA DBBR DBBN DCCV DCDB DBBY DDCA DCDH DCDL DCDS DBBS DCDV DDFA VO1 VOLTAGE 3.3V 3.3V 3.3V 3.3V 3.0V 3.0V 3.0V 2.9V 2.85V 2.85V 2.85V 2.85V 2.85V 2.85V 2.8V 2.8V 2.8V 2.8V 2.8V 2.7V 2.7V 2.5V 2.5V 2.5V 1.85V 1.85V 1.8V 1.8V 1.5V 1.5V 1.5V 1.5V VO2 VOLTAGE 3.3V 2.8V 2.5V 1.8V 3.3V 3.0V 2.7V 2.9V 3.3V 2.85V 2.8V 2.5V 1.85V 1.8V 3.3V 3.0V 2.6V 1.8V 1.5V 1.85V 1.8V 2.8V 2.0V 1.8V 2.9V 1.85V 2.8V 1.8V 2.9V 2.8V 1.8V 1.5V TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN 10 Ld 3x3 DFN PKG. DWG. # L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C L10.3x3C
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FN9245.3 March 11, 2008
ISL9014
Absolute Maximum Ratings
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V VO1, VO2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN+0.3)V
Thermal Information
Thermal Resistance (Notes 4, 5) JA (C/W) JC (C/W) 10 Ld 3x3 DFN Package . . . . . . . . . . . 50 10 Junction Temperature Range . . . . . . . . . . . . . . . . .-40C to +125C Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40C to +85C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40C to +85C; VIN = (VO + 1.0V) to 6.5V with a minimum VIN of 2.3V; CIN = 1F; CO = 1F; CBYP = 0.01F. SYMBOL TEST CONDITIONS MIN MAX (Note 7) TYP (Note 7) UNITS
PARAMETER DC CHARACTERISTICS Supply Voltage Ground Current
VIN Quiescent condition: IO1 = 0A; IO2 = 0A IDD1 IDD2 One LDO active Both LDO active @ +25C
2.3
6.5
V
25 45 0.1 1.9 1.6 2.1 1.8
40 60 1.0 2.3 2.0 +1.8
A A A V V % %/V % % mA mA
Shutdown Current UVLO Threshold
IDDS VUV+ VUV-
Regulation Voltage Accuracy Line Regulation Load Regulation
Variation from nominal voltage output, VIN = VO +0.5V to 5.5V, TJ = -40C to +125C VIN = (VOUT + 1.0V relative to highest output voltage) to 5.5V IOUT = 100A to 150mA IOUT = 100A to 300mA
-1.8 -0.2 0 0.1
0.2 0.7 1.0
Maximum Output Current
IMAX
VO1: Continuous VO2: Continuous
300 300 350 475 125 300 250 200 145 110 600 200 500 400 325
Internal Current Limit Dropout Voltage (Note 6)
ILIM VDO1 VDO2 VDO3 VDO4 IO = 150mA; VO > 2.1V IO = 300mA; VO < 2.5V IO = 300mA; 2.5V VO 2.8V IO = 300mA; VO > 2.8V
mA mV mV mV mV C C
Thermal Shutdown Temperature
TSD+ TSD-
AC CHARACTERISTICS Ripple Rejection IO = 10mA, VIN = 2.8V(min), VO = 1.8V, CBYP = 0.1F @ 1kHz @ 10kHz @ 100kHz 70 55 40 dB dB dB
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FN9245.3 March 11, 2008
ISL9014
Electrical Specifications
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40C to +85C; VIN = (VO + 1.0V) to 6.5V with a minimum VIN of 2.3V; CIN = 1F; CO = 1F; CBYP = 0.01F. (Continued) SYMBOL TEST CONDITIONS IO = 100A, VO = 1.5V, TA = +25C, CBYP = 0.1F BW = 10Hz to 100kHz MIN MAX (Note 7) TYP (Note 7) 30 UNITS VRMS
PARAMETER Output Noise Voltage
DEVICE START-UP CHARACTERISTICS Device Enable Time LDO Soft-Start Ramp Rate EN1, EN2 PIN CHARACTERISTICS Input Low Voltage Input High Voltage Input Leakage Current Pin Capacitance NOTES: 6. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V. 7. Parts are 100% tested at +25C. Temperature limits established by characterization and are not production tested. VIL VIH IIL, IIH CPIN Informative 5 -0.3 1.4 0.5 VIN + 0.3 0.1 V V A pF tEN tSSR Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO(nom) Slope of linear portion of LDO output voltage ramp during start-up 250 30 500 60 s s/V
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FN9245.3 March 11, 2008
ISL9014 Typical Performance Curves
0.8 0.6 OUTPUT VOLTAGE, VO (%) 0.4 0.2 -40C 0.0 +25C -0.2 -0.4 -0.6 -0.8 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2 6.6 INPUT VOLTAGE (V) +85C VO = 3.3V ILOAD = 0mA OUTPUT VOLTAGE CHANGE (%) 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 +85C -0.04 -0.06 -0.08 -0.10 0 50 100 150 200 250 300 350 400 +25C -40C VIN = 3.8V VO = 3.3V
LOAD CURRENT - IO (mA)
FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT)
0.10 0.08 OUTPUT VOLTAGE CHANGE (%) 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 VIN = 3.8V VO = 3.3V ILOAD = 0mA
FIGURE 2. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
3.4 IO = 0mA VO = 3.3V
3.3 OUTPUT VOLTAGE, VO (V)
3.2 IO = 150mA 3.1 IO = 300mA 3.0
2.9
2.8 3.1 3.6 4.1 4.6 5.1 5.6 6.1 6.5 INPUT VOLTAGE (V)
FIGURE 3. OUTPUT VOLTAGE CHANGE vs TEMPERATURE
FIGURE 4. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT)
350 300 250 VO = 2.8V 200 VO = 3.3V 150 100 50 0 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 400
2.9 IO = 0mA 2.8 DROPOUT VOLTAGE, VDO (mV) 4.1 4.6 5.1 5.6 6.1 6.5 INPUT VOLTAGE (V) OUTPUT VOLTAGE, VO (V) VO2 = 2.8V
2.7 IO = 150mA 2.6 IO = 300mA 2.5
2.4
2.3
2.6
3.1
3.6
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (VO2 = 2.8V)
FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT
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FN9245.3 March 11, 2008
ISL9014 Typical Performance Curves
175 VO1 = 3.3V 150 DROPOUT VOLTAGE, VDO (mV) GROUND CURRENT (A) 125 +85C 100 75 50 25 0 +25C -40C 50 +125C 45 +25C -40C
(Continued)
55
40
35 VO1 = 3.3V VO2 = 2.8V IO (BOTH CHANNELS) = 0A
30
0
25
50
75
100
125
150
175
200
25
3.0
3.5
4.0
4.58
5.0
5.5
6.0
6.5
OUTPUT LOAD (mA)
INPUT VOLTAGE (V)
FIGURE 7. VO1 DROPOUT VOLTAGE vs LOAD CURRENT
FIGURE 8. GROUND CURRENT vs INPUT VOLTAGE
200 180 160 GROUND CURRENT (A) 140 120 -40C 100 80 60 40 20 0 0 50 100 150 200 250 300 350 400 LOAD CURRENT (mA) VIN = 3.8V VO1 = 3.3V VO2 = 2.8V +85C GROUND CURRENT (A)
55
50
+25C
45
40
35 VIN = 3.8V VO = 3.3V ILOAD = 0A BOTH OUTPUTS ON 25 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125
30
FIGURE 9. GROUND CURRENT vs LOAD
FIGURE 10. GROUND CURRENT vs TEMPERATURE
5 4 VOLTAGE (V) 3 2 1 VIN VO1
VO1 = 3.3V VO2 = 2.8V IL1 = 300mA IL2 = 300mA 3 2 1 0 5 0
VO2 (10mV/DIV) VIN = 5.0V VO1 = 3.3V VO2 = 2.8V IL1 = 300mA IL2 = 300mA CL-1, CL-2 = 1F CBYP = 0.01F
VO2
VEN (V)
0
VO1 (V)
0
1
2
3
4
5 TIME (s)
6
7
8
9
10
0
100
200
300
400
500
600
700
800
900 1000
TIME (s)
FIGURE 11. POWER-UP/POWER-DOWN
FIGURE 12. TURN-ON/TURN-OFF RESPONSE
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FN9245.3 March 11, 2008
ISL9014 Typical Performance Curves
(Continued)
VO2 = 2.8V ILOAD = 300mA CLOAD = 1F CBYP = 0.01F 4.2V 3.5V
VO = 3.3V ILOAD = 300mA CLOAD = 1F CBYP = 0.01F 4.3V 3.6V
10mV/DIV
10mV/DIV
400s/DIV
400s/DIV
FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT
FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT
100 90 VO (25mV/DIV) 80 70 VO = 1.8V VIN = 2.8V PSRR (dB) 60 50 40 30 ILOAD 100A 10 100s/DIV 0 0.1 1k 10k FREQUENCY (Hz) 100k 1M 20 VIN = 3.6V VO = 1.8V IO = 10mA CBYP = 0.1F CLOAD = 1F
300mA
FIGURE 15. LOAD TRANSIENT RESPONSE
FIGURE 16. PSRR vs FREQUENCY
1000
SPECTRAL NOISE DENSITY (nV/Hz)
100
10 VIN = 3.6V VO = 1.8V ILOAD = 10mA 1 CBYP = 0.1F CIN = 1F CLOAD = 1F 0.1 10
100
1k 10k FREQUENCY (Hz)
100k
1M
FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY
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FN9245.3 March 11, 2008
ISL9014 Pin Description
PIN NUMBER 1 2 3 4 PIN NAME VIN EN1 EN2 CBYP Analog I/O Low Voltage Compatible CMOS Input Low Voltage Compatible CMOS Input Analog I/O TYPE Supply Voltage/LDO Input: Connect a 1F capacitor to GND. LDO-1 Enable. LDO-2 Enable. Reference Bypass Capacitor Pin: Optionally connect capacitor of value 0.01F to 1F between this pin and GND to tune in the desired noise and PSRR performance. No Connection GND is the connection to system ground. Connect to PCB Ground plane. LDO-2 Output: Connect capacitor of value 1F to 10F to GND (1F recommended). LDO-1 Output: Connect capacitor of value 1F to 10F to GND (1F recommended). DESCRIPTION
5, 7, 8 6 9 10
NC GND VO2 VO1
NC Ground Analog I/O Analog I/O
Typical Application
ISL9014 VIN (2.3V TO 6.5V) ON ENABLE 1 OFF ON ENABLE 2 OFF 1 2 3 4 CBYP 5 C1 C2 NC NC 6 GND C3 C4 10 VIN EN1 EN2 VO1 9 VO2 8 NC 7 VOUT 2 VOUT 1
C1, C3, C4: 1F X5R CERAMIC CAPACITOR C2: 0.1F X5R CERAMIC CAPACITOR
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FN9245.3 March 11, 2008
ISL9014 Block Diagram
VIN
IS1 VREF 1V QEN1 VO2 TRIM LDO ERROR AMPLIFIER VO1 VO1
~1.0V
LDO-1 LDO-2 QEN1 QEN2
IS1 EN1 EN2
CONTROL LOGIC
UVLO
BANDGAP AND TEMPERATURE SENSOR
IS2
VOLTAGE REFERENCE GENERATOR
1.00V
GND
CBYP
Functional Description
The ISL9014 contains all circuitry required to implement two high performance LDOs. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9014 adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, smart thermal shutdown protection, staged turn-on and soft-start. Smart Thermal shutdown protects the device against overheating. Staged turn-on and soft-start minimize start-up input current surges without causing excessive device turn-on time.
mode. During this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1A. When one or both of the enable pins are asserted, the device first polls the output of the UVLO detector to ensure that VIN voltage is at least about 2.1V. Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry power-up. Once the references are stable, a fast-start circuit quickly charges the external reference bypass capacitor (connected to the CBYP pin) to the proper operating voltage. After the bypass capacitor has been charged, the LDOs power-up. If EN1 is brought high, and EN2 goes high before the VO1 output stabilizes, the ISL9014 delays the VO2 turn-on until the VO1 output reaches its target level. If EN2 is brought high, and EN1 goes high before VO2 starts its output ramp, then VO1 turns on first and the ISL9014
Power Control
The ISL9014 has two separate enable pins (EN1 and EN2) to individually control power to each of the LDO outputs. When both EN1 and EN2 are low, the device is in shutdown
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FN9245.3 March 11, 2008
ISL9014
delays the VO2 turn-on until the VO1 output reaches its target level. If EN2 is brought high, and EN1 goes high after VO2 starts its output ramp, then the ISL9014 immediately starts to ramp up the VO1 output. If both EN1 and EN2 are brought high at the same time, the VO1 output has priority, and is always powered up first. During operation, whenever the VIN voltage drops below about 1.8V, the ISL9014 immediately disables both LDO outputs. When VIN rises back above 2.1V, the device re-initiates its start-up sequence and LDO operation will resume automatically.
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9014 provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1F to 10F output capacitor that has a tolerance better than 20% and ESR less than 200m. The design is performance-optimized for a 1F capacitor. Unless limited by the application, use of an output capacitor value above 4.7F is not recommended as LDO performance improvement is minimal. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30s/V to minimize current surge. The ISL9014 provides short-circuit protection by limiting the output current to about 475mA. Each LDO uses an independently trimmed 1V reference. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory.
Reference Generation
The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. The filter includes the external capacitor connected to the CBYP pin. A 0.01F capacitor connected CBYP implements a 100Hz lowpass filter, and is recommended for most high performance applications. For the lowest noise application, a 0.1F or greater CBYP capacitor should be used. This filters the reference noise to below the 10Hz to 1kHz frequency band, which is crucial in many noise-sensitive applications. The bandgap generates a zero temperature coefficient (TC) voltage for the reference divider. The reference divider provides the regulation reference and other voltage references required for current generation and over-temperature detection. The current generator outputs references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination.
Overheat Detection
The bandgap outputs a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about +145C, one or both of the LDOs momentarily shut down until the die cools sufficiently. In the overheat condition, only the LDO sourcing more than 50mA will be shut off. This does not affect the operation of the other LDO. If both LDOs source more than 50mA and an overheat condition occurs, both LDO outputs are disabled. Once the die temperature falls back below about +110C, the disabled LDO(s) are re-enabled and soft-start automatically takes place.
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FN9245.3 March 11, 2008
ISL9014 Dual Flat No-Lead Plastic Package (DFN)
2X 0.10 C A A D 2X 0.10 C B
L10.3x3C
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A
E
MIN 0.85 -
NOMINAL 0.90 0.20 REF
MAX 0.95 0.05
NOTES -
A1 A3 b D
6 INDEX AREA TOP VIEW B
0.20
0.25 3.00 BSC
0.30
5, 8 -
D2
// 0.10 C 0.08 C
2.33
2.38 3.00 BSC
2.43
7, 8 -
E E2 e k L 0.20 0.35 1.59
A C SEATING PLANE SIDE VIEW A3
1.64 0.50 BSC 0.40 10 5
1.69
7, 8 -
0.45
8 2 3 Rev. 1 4/06
D2 (DATUM B) 1 2 D2/2
7
8
N Nd NOTES:
NX k E2
6 INDEX AREA (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
E2/2 NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) 9L 5 0.10 M C A B
6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2.
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN9245.3 March 11, 2008

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